Intel teases next-gen Meteor Lake, Arrow Lake and Lunar Lake CPUs at Hot Chips 34

A slight peep into the upcoming Meteor Lake, Arrow Lake and Lunar Lake chips

At Hot Chips 34, a symposium on high-performing chips, Intel had a lot of new developments to share. It showcased its newest architectural and packaging developments to manufacture 2.5D and 3D tile-based chip designs, enabling the next generation of chipsets and facilitating Moore’s Law further.

Intel’s CEO Pat Gelsinger talked about the way ahead for Intel, highlighting the upcoming Meteor Lake, Ponte Vecchio GPU, Intel Xeon D-2700 and 1700, and FPGAs, along with talking about their systems foundry model.

A Shift in the Technology

With the ongoing developments occurring in the sphere of semiconductors, there is a visible demand for a shift from the traditional foundry mindset towards a systems foundry. With the systems foundry model introduced by Intel, it can very well satiate the need to deliver a power-packed and complete immersive-digital experience. It does that by including its advanced packaging, an open-chiplet system, and software components to deliver a turnkey solution to the user. Paying heed to the industry’s demands in terms of expanding and improving process technology and tile-based designs, Intel promised further developments.

Technology will change the way we see the world in a big way in this time of change, growth, and new discoveries. As compute, connectivity, infrastructure, and AI become more common, they will continue to merge, enhance, and strengthen each other. This will open up powerful new possibilities that will shape the future of technology and help people reach new heights of achievement.

Execution of Intel’s Design Plan

At Hot Chips 34, Intel had previewed several product architectures that belongs to the next-gen technologies, giving a peak of what possibilities lie ahead in the future.

It talked about Meteor Lake, Arrow Lake, and Lunar Lake CPUs that will “completely change the game for personal computers” by enhancing the manufacturing, performance, and power capabilities with their tile-based chip designs. It is done by stacking the standalone CPU, GPU, SoC, and I/O tiles in 3D configurations by making use of Intel’s Foveros interconnect technology. This development was reverberated due to the great support the industry showed for the open Universal Chiplet Interconnect Express (UCIe™) specification that streamlines different chipset technologies by different vendors when they are integrated with advanced packaging technologies.

The Intel Data Center GPU, nicknamed Ponte Vecchio, deals with the compute density issues in AI supercomputing and HPC. OneAPI is used to streamline API abstractions and cross-architecture development, taking full advantage of Intel’s open software paradigm. Ponte Vecchio is built of multiple complicated designs that appear in tiles, coupled using a mix of integrated multi-die interconnect bridge (EMIB) and Foveros advanced packaging technology. More than 100 billion transistors may be packed into a single device with a high-speed MDFI connector, which enables the package to expand up to two stacks.

The Xeon D-2700 and 1700 series are ideal for edge use cases in 5G, IoT, corporate, and cloud applications. These chips are also good examples of tile-based design because of features like 100G Ethernet with a flexible packet processor, inline crypto acceleration, time-coordinated computing (TCC), time-sensitive networking (TSN), and in-built optimization for artificial intelligence (AI) procedures.

Field Programmable Gate Arrays (FPGAs) are a strong and adaptable tool for hardware acceleration, especially in RF applications. By merging digital and analogue chiplets from multiple process nodes and foundries, Intel has saved development time and increased developer flexibility. Intel will soon disclose its chiplet-based findings.

Stay tuned to this space to get more info on this development that we will share in the upcoming days. Till then, stay techno & ill-active!